<?xml version="1.0" encoding="utf-8"?>
<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.1//EN" "http://www.w3.org/TR/xhtml11/DTD/xhtml11.dtd">
<html xmlns="http://www.w3.org/1999/xhtml"><head><link rel="stylesheet" type="text/css" href="insn.css"/><meta name="generator" content="iform.xsl"/><title>PRFH (vector plus immediate)</title></head><body><table style="margin: 0 auto;"><tr><td><div class="topbar"><a href="index.html">Base Instructions</a></div></td><td><div class="topbar"><a href="fpsimdindex.html">SIMD&amp;FP Instructions</a></div></td><td><div class="topbar"><a href="sveindex.html">SVE Instructions</a></div></td><td><div class="topbar"><a href="mortlachindex.html">SME Instructions</a></div></td><td><div class="topbar"><a href="encodingindex.html">Index by Encoding</a></div></td><td><div class="topbar"><a href="shared_pseudocode.html">Shared Pseudocode</a></div></td><td><div class="topbar"><a href="notice.html">Proprietary Notice</a></div></td></tr></table><hr/><h2 class="instruction-section">PRFH (vector plus immediate)</h2><p>Gather prefetch halfwords (vector plus immediate)</p>
      <p class="aml">Gather prefetch of halfwords from the active memory addresses generated by a vector base plus immediate index. The index is a multiple of 2 in the range 0 to 62. Inactive addresses are not prefetched from memory.</p>
      <p class="aml">The &lt;prfop&gt; symbol specifies the prefetch hint as a combination of three options: access type PLD for load or PST for store; target cache level L1, L2 or L3; temporality (KEEP for temporal or STRM for non-temporal).</p>
      <p class="aml">This instruction is illegal when executed in Streaming SVE mode, unless FEAT_SME_FA64 is implemented and enabled.</p>
    
    <p class="desc">
      It has encodings from 2 classes:
      <a href="#iclass_32_elem">32-bit element</a>
       and 
      <a href="#iclass_64_elem">64-bit element</a>
    </p>
    <h3 class="classheading"><a id="iclass_32_elem"/>32-bit element</h3><div class="regdiagram-32"><table class="regdiagram"><thead><tr><td>31</td><td>30</td><td>29</td><td>28</td><td>27</td><td>26</td><td>25</td><td>24</td><td>23</td><td>22</td><td>21</td><td>20</td><td>19</td><td>18</td><td>17</td><td>16</td><td>15</td><td>14</td><td>13</td><td>12</td><td>11</td><td>10</td><td>9</td><td>8</td><td>7</td><td>6</td><td>5</td><td>4</td><td>3</td><td>2</td><td>1</td><td>0</td></tr></thead><tbody><tr class="firstrow"><td class="l">1</td><td>0</td><td>0</td><td>0</td><td>0</td><td>1</td><td class="r">0</td><td class="lr">0</td><td class="lr">1</td><td class="l">0</td><td class="r">0</td><td colspan="5" class="lr">imm5</td><td class="l">1</td><td>1</td><td class="r">1</td><td colspan="3" class="lr">Pg</td><td colspan="5" class="lr">Zn</td><td class="lr">0</td><td colspan="4" class="lr">prfop</td></tr><tr class="secondrow"><td colspan="7"/><td class="droppedname">msz&lt;1&gt;</td><td class="droppedname">msz&lt;0&gt;</td><td colspan="2"/><td colspan="5"/><td colspan="3"/><td colspan="3"/><td colspan="5"/><td/><td colspan="4"/></tr></tbody></table></div><div class="encoding"><h4 class="encoding"/><a id="prfh_i_p_ai_s"/><p class="asm-code">PRFH    <a href="#sa_prfop" title="Prefetch operation specifier (field &quot;prfop&quot;) [#uimm4,PLDL1KEEP,PLDL1STRM,PLDL2KEEP,PLDL2STRM,PLDL3KEEP,PLDL3STRM,PSTL1KEEP,PSTL1STRM,PSTL2KEEP,PSTL2STRM,PSTL3KEEP,PSTL3STRM]">&lt;prfop&gt;</a>, <a href="#sa_pg" title="Governing scalable predicate register P0-P7 (field &quot;Pg&quot;)">&lt;Pg&gt;</a>, [<a href="#sa_zn" title="Base scalable vector register (field &quot;Zn&quot;)">&lt;Zn&gt;</a>.S{, #<a href="#sa_imm" title="Optional unsigned immediate byte offset, multiple of 2 [0-62], default 0 (field &quot;imm5&quot;)">&lt;imm&gt;</a>}]</p></div><p class="pseudocode">if !<a href="shared_pseudocode.html#impl-aarch64.HaveSVE.0" title="function: boolean HaveSVE()">HaveSVE</a>() then UNDEFINED;
constant integer esize = 32;
integer g = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(Pg);
integer n = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(Zn);
integer level = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(prfop&lt;2:1&gt;);
boolean stream = (prfop&lt;0&gt; == '1');
pref_hint = if prfop&lt;3&gt; == '0' then <a href="shared_pseudocode.html#Prefetch_READ" title="enumeration PrefetchHint {Prefetch_READ, Prefetch_WRITE, Prefetch_EXEC}">Prefetch_READ</a> else <a href="shared_pseudocode.html#Prefetch_WRITE" title="enumeration PrefetchHint {Prefetch_READ, Prefetch_WRITE, Prefetch_EXEC}">Prefetch_WRITE</a>;
integer scale = 1;
integer offset = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(imm5);</p>
    <h3 class="classheading"><a id="iclass_64_elem"/>64-bit element</h3><div class="regdiagram-32"><table class="regdiagram"><thead><tr><td>31</td><td>30</td><td>29</td><td>28</td><td>27</td><td>26</td><td>25</td><td>24</td><td>23</td><td>22</td><td>21</td><td>20</td><td>19</td><td>18</td><td>17</td><td>16</td><td>15</td><td>14</td><td>13</td><td>12</td><td>11</td><td>10</td><td>9</td><td>8</td><td>7</td><td>6</td><td>5</td><td>4</td><td>3</td><td>2</td><td>1</td><td>0</td></tr></thead><tbody><tr class="firstrow"><td class="l">1</td><td>1</td><td>0</td><td>0</td><td>0</td><td>1</td><td class="r">0</td><td class="lr">0</td><td class="lr">1</td><td class="l">0</td><td class="r">0</td><td colspan="5" class="lr">imm5</td><td class="l">1</td><td>1</td><td class="r">1</td><td colspan="3" class="lr">Pg</td><td colspan="5" class="lr">Zn</td><td class="lr">0</td><td colspan="4" class="lr">prfop</td></tr><tr class="secondrow"><td colspan="7"/><td class="droppedname">msz&lt;1&gt;</td><td class="droppedname">msz&lt;0&gt;</td><td colspan="2"/><td colspan="5"/><td colspan="3"/><td colspan="3"/><td colspan="5"/><td/><td colspan="4"/></tr></tbody></table></div><div class="encoding"><h4 class="encoding"/><a id="prfh_i_p_ai_d"/><p class="asm-code">PRFH    <a href="#sa_prfop" title="Prefetch operation specifier (field &quot;prfop&quot;) [#uimm4,PLDL1KEEP,PLDL1STRM,PLDL2KEEP,PLDL2STRM,PLDL3KEEP,PLDL3STRM,PSTL1KEEP,PSTL1STRM,PSTL2KEEP,PSTL2STRM,PSTL3KEEP,PSTL3STRM]">&lt;prfop&gt;</a>, <a href="#sa_pg" title="Governing scalable predicate register P0-P7 (field &quot;Pg&quot;)">&lt;Pg&gt;</a>, [<a href="#sa_zn" title="Base scalable vector register (field &quot;Zn&quot;)">&lt;Zn&gt;</a>.D{, #<a href="#sa_imm" title="Optional unsigned immediate byte offset, multiple of 2 [0-62], default 0 (field &quot;imm5&quot;)">&lt;imm&gt;</a>}]</p></div><p class="pseudocode">if !<a href="shared_pseudocode.html#impl-aarch64.HaveSVE.0" title="function: boolean HaveSVE()">HaveSVE</a>() then UNDEFINED;
constant integer esize = 64;
integer g = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(Pg);
integer n = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(Zn);
integer level = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(prfop&lt;2:1&gt;);
boolean stream = (prfop&lt;0&gt; == '1');
pref_hint = if prfop&lt;3&gt; == '0' then <a href="shared_pseudocode.html#Prefetch_READ" title="enumeration PrefetchHint {Prefetch_READ, Prefetch_WRITE, Prefetch_EXEC}">Prefetch_READ</a> else <a href="shared_pseudocode.html#Prefetch_WRITE" title="enumeration PrefetchHint {Prefetch_READ, Prefetch_WRITE, Prefetch_EXEC}">Prefetch_WRITE</a>;
integer scale = 1;
integer offset = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(imm5);</p>
  <div class="encoding-notes"/><h3 class="explanations">Assembler Symbols</h3><div class="explanations"><table><col class="asyn-l"/><col class="asyn-r"/><tr><td>&lt;prfop&gt;</td><td><a id="sa_prfop"/>
        <p>Is the prefetch operation specifier, 
      encoded in
      <q>prfop</q>:
        </p>
        <table class="valuetable">
          
            <thead>
              <tr>
                <th class="bitfield">prfop</th>
                <th class="symbol">&lt;prfop&gt;</th>
              </tr>
            </thead>
            <tbody>
              <tr>
                <td class="bitfield">0000</td>
                <td class="symbol">PLDL1KEEP</td>
              </tr>
              <tr>
                <td class="bitfield">0001</td>
                <td class="symbol">PLDL1STRM</td>
              </tr>
              <tr>
                <td class="bitfield">0010</td>
                <td class="symbol">PLDL2KEEP</td>
              </tr>
              <tr>
                <td class="bitfield">0011</td>
                <td class="symbol">PLDL2STRM</td>
              </tr>
              <tr>
                <td class="bitfield">0100</td>
                <td class="symbol">PLDL3KEEP</td>
              </tr>
              <tr>
                <td class="bitfield">0101</td>
                <td class="symbol">PLDL3STRM</td>
              </tr>
              <tr>
                <td class="bitfield">x11x</td>
                <td class="symbol">#uimm4</td>
              </tr>
              <tr>
                <td class="bitfield">1000</td>
                <td class="symbol">PSTL1KEEP</td>
              </tr>
              <tr>
                <td class="bitfield">1001</td>
                <td class="symbol">PSTL1STRM</td>
              </tr>
              <tr>
                <td class="bitfield">1010</td>
                <td class="symbol">PSTL2KEEP</td>
              </tr>
              <tr>
                <td class="bitfield">1011</td>
                <td class="symbol">PSTL2STRM</td>
              </tr>
              <tr>
                <td class="bitfield">1100</td>
                <td class="symbol">PSTL3KEEP</td>
              </tr>
              <tr>
                <td class="bitfield">1101</td>
                <td class="symbol">PSTL3STRM</td>
              </tr>
            </tbody>
          
        </table>
      </td></tr></table><table><col class="asyn-l"/><col class="asyn-r"/><tr><td>&lt;Pg&gt;</td><td><a id="sa_pg"/>
        
          <p class="aml">Is the name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.</p>
        
      </td></tr></table><table><col class="asyn-l"/><col class="asyn-r"/><tr><td>&lt;Zn&gt;</td><td><a id="sa_zn"/>
        
          <p class="aml">Is the name of the base scalable vector register, encoded in the "Zn" field.</p>
        
      </td></tr></table><table><col class="asyn-l"/><col class="asyn-r"/><tr><td>&lt;imm&gt;</td><td><a id="sa_imm"/>
        
          <p class="aml">Is the optional unsigned immediate byte offset, a multiple of 2 in the range 0 to 62, defaulting to 0, encoded in the "imm5" field.</p>
        
      </td></tr></table></div><div class="syntax-notes"/>
    <div class="ps"><a id="execute"/><h3 class="pseudocode">Operation</h3>
      <p class="pseudocode"><a href="shared_pseudocode.html#impl-aarch64.CheckNonStreamingSVEEnabled.0" title="function: CheckNonStreamingSVEEnabled()">CheckNonStreamingSVEEnabled</a>();
constant integer VL = <a href="shared_pseudocode.html#impl-aarch64.CurrentVL.read.none" title="accessor: integer CurrentVL">CurrentVL</a>;
constant integer PL = VL DIV 8;
constant integer elements = VL DIV esize;
bits(PL) mask = <a href="shared_pseudocode.html#impl-aarch64.P.read.2" title="accessor: bits(width) P[integer n, integer width]">P</a>[g, PL];
bits(VL) base;

if <a href="shared_pseudocode.html#impl-aarch64.AnyActiveElement.2" title="function: boolean AnyActiveElement(bits(N) mask, integer esize)">AnyActiveElement</a>(mask, esize) then
    base = <a href="shared_pseudocode.html#impl-aarch64.Z.read.2" title="accessor: bits(width) Z[integer n, integer width]">Z</a>[n, VL];

for e = 0 to elements-1
    if <a href="shared_pseudocode.html#impl-aarch64.ActivePredicateElement.3" title="function: boolean ActivePredicateElement(bits(N) pred, integer e, integer esize)">ActivePredicateElement</a>(mask, e, esize) then
        bits(64) addr = <a href="shared_pseudocode.html#impl-shared.ZeroExtend.2" title="function: bits(N) ZeroExtend(bits(M) x, integer N)">ZeroExtend</a>(<a href="shared_pseudocode.html#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[base, e, esize], 64) + (offset &lt;&lt; scale);
        <a href="shared_pseudocode.html#impl-shared.Hint_Prefetch.4" title="function: Hint_Prefetch(bits(64) address, PrefetchHint hint, integer target, boolean stream)">Hint_Prefetch</a>(addr, pref_hint, level, stream);</p>
    </div>
  <hr/><table style="margin: 0 auto;"><tr><td><div class="topbar"><a href="index.html">Base Instructions</a></div></td><td><div class="topbar"><a href="fpsimdindex.html">SIMD&amp;FP Instructions</a></div></td><td><div class="topbar"><a href="sveindex.html">SVE Instructions</a></div></td><td><div class="topbar"><a href="mortlachindex.html">SME Instructions</a></div></td><td><div class="topbar"><a href="encodingindex.html">Index by Encoding</a></div></td><td><div class="topbar"><a href="shared_pseudocode.html">Shared Pseudocode</a></div></td><td><div class="topbar"><a href="notice.html">Proprietary Notice</a></div></td></tr></table><p class="versions">
      Internal version only: isa v33.62, AdvSIMD v29.12, pseudocode v2023-03_rel, sve v2023-03_rc3b
      ; Build timestamp: 2023-03-31T11:36
    </p><p class="copyconf">
      Copyright © 2010-2023 Arm Limited or its affiliates. All rights reserved.
      This document is Non-Confidential.
    </p></body></html>
